# How do I make a clocked Mealy sequential network with one imput(x) and one output(z), and the output

How do I compel a clocked Mealy sequential network following a while one imput(x) and one output(z), and the output is to be '0', cosmical the input is '0' subjoined a succession of correspondently two '0' inputs followed by a '1' input. these are examples of the feasible input postulates and output responses according to the inputs. X = 0 0 1 0 Z = 0 0 0 1 //following those two 0s the output allure be 1 following that. X = . . . 1 0 0 1 0 Z = . . . 0 0 0 0 1 X = . . . 0 0 0 1 0 Z = . . . 0 0 0 0 0 //but when tere are three 0s, the output wil not entertain 1. X = 0 0 1 0 0 1 0 0 0 1 0 Z = 0 0 0 1 0 0 1 0 0 0 0 and how do you guile a succession enlightener such that the output, z, allure be a ‘1’ if the input succession ends in either ‘010’ or ‘1001’, differently z allure be a ‘0’. and how do you guile a restricted avow enlightener that has one input, x, and one output, z. The output is asserted whenever the input succession ‘. . . 010 . . .’ has bee observed, as hanker as the succession ‘100’ has never been seen. how do you compel the verilog codes for this? can you guys acceleration me to compel the codes. I would unquestionably esteem for any acceleration... Thanks alot..! entertain an awful day!